The present invention relates generally to automated optical inspection (AOI) systems and particularly to an AOI system for inspecting electrical circuits such as printed circuit boards (PCBs) of any kind, including interconnect packaging substrates (ICP), flat panel displays (FPDs) and integrated circuits.
Automated optical inspection (AOI) systems are used to inspect various kinds of articles and electrical circuits, including the surfaces of FPDs, the surfaces of individual laminate layers of PCBs and ICPs prior to lamination (sometimes called inner layers), the surfaces of already laminated multi-layer PCBs and ICPs (sometimes called outer layers), the surfaces of electrical circuits having solder paste deposits formed thereon, and electrical circuits having electronic components mounted thereon. In general, electrical circuits such as PCBs, ICPS, FPDs and integrated circuits, are formed by selectively depositing a reflective conductor on a substrate.
In conventional AOI systems portions of the surface of an electrical circuit under inspection are successively illuminated with a thin line of intense light. Alternatively, the surface may be illuminated by a scanning laser beam. The intensity of reflected light, or of fluorescent light, in response to the illumination, is detected and registered for elemental spatial portions over the X-Y plane of the surface of the circuit to form an image of the electrical circuit surface. The image is suitably processed and analyzed with reference to a non-defective image, for example an image derived from a Computer Aided Drawing or Manufacturing (CAD or CAM) data base in order to locate the presence of defects in the electrical circuit.
One general aspect of the present invention relates to a system and methods for inspecting an electrical circuit for defects employing a three-dimensional topographical representation of an electrical circuit under inspection. The topology representation is processed and analyzed to detect the presence of defects in the planar geometric shape of the electrical circuit. Optionally, the height information is also processed to determine the presence of defects at selected locations along the surface of the electrical circuit.
In accordance with an embodiment of the invention, height data in the topology representation is transformed into a reduced information mapping of the electrical circuit indicating the planar locations, that is location in an X,Y plane, of electrical circuit features having a predetermined height attribute. In other words, a volume representation of height is transformed into a representation of planar location. For example, the reduced information mapping may appear as a planar map of the locations of any portions of the electrical circuit that are either raised or depressed with respect to the surface of a substrate. Optionally, the reduced information mapping differentiates between those portions that are raised with respect to the surface of the substrate and those portions that are depressed with respect to the surface.
Such a reduced information mapping is analyzed by a defect analyzer with reference to a corresponding representation of a known non-defective electrical circuit determine the presence of defects in the electrical circuit. The representation of a non-defective circuit may be obtained either by acquiring a representation of a known to be non-defective electrical circuit, or by derivation from a CAD or CAM computer file. Typically analysis includes confirming that all elements forming the electrical circuit are present, that the elements are properly formed and that no extraneous elements are present in the circuit.
In accordance with another embodiment of the present invention, the topology representation, or selected parts thereof, is provided to a height processor operative to analyze the topology representation, or selected parts thereof, for height defects. Height defects may include, for example, conductors and parts of conductors (hereinafter referred to together as xe2x80x9cconductorsxe2x80x9d for the sake of generality) having a height that is different from a specified height, or holes whose depth is different than a specified depth. Optionally, analysis of height defects may include distinguishing between real height defects, such as an undesired formation of a copper conductor, and non-height defects such as dust. In accordance with an embodiment of the invention, the height processor analyzes only selected portions of the electrical circuit which have been indicated as necessitating height processing. Such indication may be provided by the defect analyzer, for example based on defects in the planar formation of an electrical circuit, or by an input from a CAM reference indicating a region of the electrical circuit requiring inspection for possible height defects.
In accordance with an embodiment of the invention, height detection can be carried out using illumination provided by any suitable coherent or non-coherent, monochromatic or polychromatic light source, or any other suitable source of electromagnetic radiation.